The present invention relates to a binary coded decimal (BCD) adder circuit.
Binary coded decimal numbers are used to represent decimal numbers in a form readily understood by both man (decimal) and computer (binary). There are sixteen possible bit combinations using four binary bits, but only ten are valid BCD digits. Therefore, when two BCD digits are added and the sum digit exceeds nine, that sum digit must be adjusted to a valid BCD digit. This is generally done by adding the constant 0110.sub.2 (6.sub.10) to the sum.
Traditionally, BCD adder circuits have used logic to detect whether a BCD sum should be adjusted after the addition has been completed. For example, whenever the unadjusted sum of two BCD digits produced a carry-out (i.e., when the sum exceeds fifteen), the sum was corrected by adding 0110.sub.2. Also, an adjustment was needed whenever bit positions 8 and 4 of the BCD sum were both one's (values 12.sub.10 -15.sub.10) or when bit positions 8 and 2 were both one's (values 10.sub.10 and 11.sub.10).
Traditional BCD adder circuits, for example, such as the circuit 10 shown in FIG. 1, use standard four-bit binary adders to add two BCD digits to produce an intermediate sum (Z.sub.8,Z.sub.4, Z.sub.2, Z.sub.1). The adder circuit also includes correction logic for each intermediate sum digit greater than nine. In the circuit shown in FIG. 1, a first four-bit operand, bits a(0).sub.8 to a(0).sub.1, and a second four-bit operand, bits b(0).sub.8 to b(0).sub.1, are input in parallel to full adder 15 along with the C.sub.in or carry-in bit. The output from full adder 15 includes a four-bit sum vector Z (Z.sub.8 to Z.sub.1) and a carry-out C.sub.out. If C.sub.out is "1" or if either Z.sub.8 and Z.sub.4 are both "1" (AND gate 20) or Z.sub.8 and Z.sub.2 are both "1" (AND gate 25), the BCD adder circuit 10 produces a C(0).sub.out BCD carry from OR gate 30 and the sum vector Z is corrected by adding a value of "0110.sub.2 " to the sum vector Z. When C(0).sub.out is a "1" the B input of second full adder 35 receives a "0110.sub.2 " value while the sum vector Z is received at the A input of full adder 35. The output of full adder 35, S(0).sub.8 to S(0).sub.1, is the adjusted BCD sum of the original two operands.
As is apparent, traditional BCD adder circuits of present advanced VLSI technology, utilizing a carry-propagate full adder circuit such as 10, have a great amount of delay associated with them due to the display associated with propagation of carries through the adder circuitry (15, 35) and the delay associated with the correction circuitry (gates 20, 25, and 30). The delay associated with traditional carry-propagate full adder circuits, such as 15 and 35, is equal to: EQU Delay=log.sub.2 (operand width, i.e., number of bits per operand).
Therefore, the delay associated with adders 10 and 35 is equal to log.sub.2 (4), or two units of delay. The delay associated with the correction circuitry is equal to two units of delay since there are two gate levels to the circuit for a total delay of four units for the adder of FIG. 1. As the width of the operand increases, for example, when two 32-bit operands are to be added, the associated delay also increases. A traditional BCD adder circuit would require eight stages of carry-propagate full adders plus associated correction circuitry to perform the addition of two 32-bit operands, and thus, the associated delay could be as high as thirty-two units for this adder circuit.